1. Field of the Invention
The present disclosure relates to a packaging process, and more particularly, to a package structure having an electronic element embedded therein and a method for fabricating the package structure.
2. Description of Related Art
Along with the development of semiconductor technologies, various types of packages have been developed for semiconductor products. Particularly, chip scale packages have been developed to meet the miniaturization requirement. A chip scale package is characterized in that its size is substantially equal to or slightly larger than a chip.
FIGS. 1A to 1H are schematic cross-sectional views showing a method for fabricating a semiconductor package 1 according to existing prior art.
Referring to FIG. 1A, a first carrier 10a having a bonding layer 100 is provided, and a plurality of semiconductor elements 11 are disposed on the bonding layer 100. Each of the semiconductor elements 11 has an active surface 11a bonded to the bonding layer 100 and an inactive surface 11b opposite to the active surface 11a. The active surface 11a of the semiconductor element 11 has a plurality of electrode pads 110.
Referring to FIG. 1B, an encapsulant 13 is formed on the bonding layer 100 to encapsulate the semiconductor elements 11. The encapsulant 13 has a first surface 13a facing the bonding layer 100 and a second surface 13b opposite to the first surface 13a. Further, a second carrier 10b is disposed on the second surface 13b of the encapsulant 13.
Referring to FIG. 1C, the first carrier 10a and the bonding layer 100 are removed to expose the first surface 13a of the encapsulant 13 and the active surfaces 11a of the semiconductor elements 11.
Referring to FIG. 1D, a circuit structure 12 is formed on the first surface 13a of the encapsulant 13 and the active surfaces 11a of the semiconductor elements 11, and electrically connected to the electrode pads 110 of the semiconductor elements 11.
Referring to FIG. 1E, a third carrier 10c is disposed on the circuit structure 12, and then the second carrier 10b is removed. Thereafter, a laser drilling process is performed to form a plurality of through holes 140 penetrating the encapsulant 13 and exposing a portion of the circuit structure 12.
Referring to FIG. 1F, an electroplating process is performed to form in the through holes 140 a plurality of conductive posts 14 electrically connected to the circuit structure 12 exposed from the encapsulant 13.
Referring to FIG. 1G, a redistribution layer 15 is formed on the second surface 13b of the encapsulant 13 and electrically connected to the conductive posts 14.
Referring to FIG. 1H, the third carrier 10c is removed and a singulation process is performed. Further, a plurality of conductive elements 17 such as solder balls are formed on and electrically connected to the circuit structure 12.
In the above-described method, the laser drilling process for forming the through holes 140 is time-consuming, especially when the number of the through holes 140 is large. Further, during the laser drilling process, residues easily accumulate on the bottom of the through holes 140. Accordingly, a cleaning process is required before the electroplating process is performed to form the conductive posts 14 in the through holes 140, thus increasing the number of fabrication steps and complicating the fabrication processes.
Furthermore, the laser drilling process results in uneven wall surfaces of the through holes 140. As such, during subsequent electroplating processes, a conductive material cannot be effectively attached to the wall surfaces of the through holes 140 and easily delaminates from the wall surfaces of the through holes 140, thereby reducing the product reliability of the semiconductor package 1.
In addition, since the laser drilling process is performed on the second surface 13b of the encapsulant 13 that is not transparent, a laser drilling device cannot detect the circuit structure 12 under the encapsulant 13. Therefore, special processes and devices are required for drilling alignment. As such, the number of fabrication steps and the fabrication costs are further increased.
Also, a laser beam used in the laser drilling process produces a heat affected zone. That is, if the position of the through holes 140 is close to the semiconductor elements 11, high heat resulted from the laser beam will damage the semiconductor elements 11. Therefore, a certain distance must be kept between the conductive posts 14 and the semiconductor elements 11, thus hindering miniaturization of the semiconductor package 1.
In addition, the above-described method includes multiple carrier bonding/removing processes (including, for example, the first, second and third carriers 10a, 10b, 10c). Theses processes complicate the fabrication process and increase the fabrication time and costs.
Therefore, there is a need to provide a package structure and a fabrication method thereof so as to overcome the above-described drawbacks.